About Us

What We Do:

Whether dealing with High speed DDR memory, Pentium or PPC processor bus designs or Gigabit Serial links, all require predictable, precise designs to guarantee reliable operation.

Reliable operation is impacted by SI through
•Timing erosion
•Product lifetime degradations due to voltage Over and Undershoot
•Excessive EMI due to misunderstanding the cause and effect of SI
Timing analysis that only incorporates classic internal digital elements misses critical factors impacting the actual overall timing budget. Timing shifts can be caused by crosstalk, Jitter, the impact of your PCB stackup as well as termination and stub effects.

Electronic Expertise has experience and tools to attack each of these design challenges.

Success stories include all of the following arenas
•2.5 - 10.0 Gigabit PCB Serial Diff. Data Channel design, Optical / Electrical interfacing
•2D & 3D structure modeling (PCB & Packages-breakouts, vias, bond wires & micro-structures)
•3D S-Parameter Package & Via design / analysis
•QDRSRAM, RLDRAM, ASRAM, DDR-SDRAM, architectures at 667+ MHz
•Custom memory interfaces
•3.5 GigBit Back Plane Analysis & Proprietary back plane designs & system loss
•PCI Express Bus design
•Processor Bus Design, PPC603/750/405(100+MHZ), 29040, i960, 80xx
•Technologies include: CML, CMOS, PECL, LVDS, SSTL, HSTL, BTL, GTL, TTL
•EMI sensitivity analysis
•Spice to IBIS conversions up to 10Gbit

Electronic Expertise can help your company at any stage of the design process. Common ways we can assist your company:

•Up front architectural and “what if” Signal Integrity design & analysis
•Direct interaction with the PCB or Packaging creation process, closing the loop between theoretical and actual achievement of timing and electrical margins
•Post design debug of problematic digital designs
Training personnel about the effects and strategies to overcome signal integrity issues

2012 © Electronic Expertise Ltd. | 1928 Mariposa, Boulder CO 80302 USA
phone: 303-464-8603 | fax: 303-465-0710